A Logic Nanotechnology Featuring Strained-Silicon

S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic (+7 others)
2004 IEEE Electron Device Letters  
Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology [1]. Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si 1 Ge in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSEFT. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type
more » ... T and enhance electron mobility. Unlike past strained-Si work, 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies. Index Terms-CMOS, metal-oxide-semiconductor field-effect transistors (MOSFET), strained-silicon (Si).
doi:10.1109/led.2004.825195 fatcat:7qej3ehzebae7eafb6kqrrctni