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2010 International Conference on Microelectronics
Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of architectures containing hundreds of processor cores, and involving hundreds of SC THREADs to be scheduled. In this paper, we describe a general modeling strategydoi:10.1109/icm.2010.5696160 fatcat:vkqg7z7jyfarjgqyh773exub4y