The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps

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... us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic A TPG engine is developed. Clustering ofpaths has been done in order to improve the test set quality. Implications were used to identi@ the untestable paths. Finally an incremental propagation based A TPG is used for transition faults. Results for ISCAS'85 and full-scan ISCAS'89 benchmark circuits show that the filtered nonrobust path set can be reduced to 40% smaller than the conventional path set without losing delay defect coverage. Clustering reduces vector size in average by about 40%. robustly, the region of overlap is also tested robustly. If L"" is greater than some preset threshold, then the delay Paper 23.2 584 ITC INTERNATIONAL TEST CONFERENCE 0-7803-81 06-8/03 $1 7.00