This paper describes the impact of crosstalk noise on low power design techniques based on voltage scaling. It is shown that this power saving strategy aggravates the crosstalk noise problem and reduces circuit noise immunity. A new energy-e cient, noise-tolerant dynamic circuit technique is presented to address this problem. In a 0.35m CMOS technology and at a given supply voltage, the proposed t e chnique provides an improvement in noiseimmunity of 1.8Xfor an AND gate and 2.5Xfor an adder

more »

... y chain over domino at the same speed. We use this fact to operate the noise-tolerant circuit at a lower supply voltage to obtain energy savings of about 30, while expending 30 more a r e a. Also, to achieve a given noise immunity, the proposed technique consumes 40 less energy compared to existing noise-tolerance t e chniques. Impact of V dd ; V T scaling on Crosstalk Noise A v ery popular low p o w er strategy is the scaling of the supply voltage V dd 1 , 2 , 3 , 4 . One can obtain large savings