Reducing NoC and Memory Contention for Manycores [chapter]

Vishwanathan Chandru, Frank Mueller
2016 Lecture Notes in Computer Science  
Platforms consisting of many computing cores have become the mainstream in high performance computing, general purposecomputing and, lately, embedded systems. Such systems provide increased processing power and system availability, but often impose latencies and contention for memory accesses as multiple cores try to reference data at the same time. This may result in sub-optimal performance unless special allocation policies are employed. On a multi-processor board with 50 or more processing
more » ... res, the NoC (Network On Chip) adds to this challenge. This work evaluates the impact of bank-aware and controller-aware allocation on NoC contention. Experiments show that targeted memory allocation results in reduced execution times and NoC contention, the latter of which has not been studied before at this scale. banks. Address Mapping Address translation is straight forward. The physical address has 36 bits [8] . Per the documentation and configuration register values, address hashing is per-
doi:10.1007/978-3-319-30695-7_22 fatcat:ntdpzv2epnevtpdmysb5hb5dr4