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A 3d-audio reconfigurable processor
2010
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10
Various multimedia communication systems based on 3D-Audio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in the literature follow a PC-based approach that introduces processing bottlenecks and excessive power consumption. In order to alleviate these problems, we propose a reconfigurable 3D-Audio processor that can record and render sound sources concurrently. Audio recording and rendering are performed by two hardware
doi:10.1145/1723112.1723131
dblp:conf/fpga/TheodoropoulosKG10
fatcat:alhzhrlvpbcnthy3oygjsawicm