Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU

William J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen (+9 others)
1995 Digital technical journal of Digital Equipment Corporation  
A 300-MHz, custom 64-bit VLSI, second-generation Alpha CPU chip has been developed. The chip was designed in a 0.5-um CMOS technology using four levels of metal. The die size is 16.5 mm by 18.1 mm, contains 9.3 million transistors, operates at 3.3 V, and supports 3.3-V/5.0-V interfaces. Power dissipation is 50 W. It contains an 8-KB instruction cache; an 8-KB data cache; and a 96-KB unified second-level cache. The chip can issue four instructions per cycle and delivers 1,200 mips/600 MFLOPS
more » ... k). Several noteworthy circuit and implementation techniques were used to attain the target operating frequency.
dblp:journals/dtj/BowhillBBBBCDEFGJKLLMMPSSST95 fatcat:sk6wveyqwrbd7kdy2a5twmdnve