Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation

T. Takayanagi, J.L. Shin, J. Su, A.S. Leon
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)  
A processor core, originally designed in a 0.5pm AI process, is redesigned for a 0 . 1 3~ Cu process to create a dual-core processor with IMB integrated L2 cache, offering an efficient performance to power ratio for compute-dense sever applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.
doi:10.1109/icicdt.2004.1309933 fatcat:psdvq55a7zhbjjqw6zl5ji6pai