A language for compositional specification and verification of finite state hardware controllers
Proceedings of the IEEE
SML is a language for describing complexfinite state hardware controllers. It provides many of the standard control structures found in modern programming languages. The state tables produced by the SML compiler can be used as input to a temporal logic model checker that can automatically determine whether a specification in the logic CTL is satisfied. We describe extensions to SML for the design of modular controllers. These extensions allow a compositional approach to model checking which can
... substantially reduce its complexity. To demonstrate our methods, we discuss the specification and verification of a simple CPU controller. David E. Long received the B.S. degree in computer science from the California Institute of Technology, Pasadena, in 1987. He is currently enrolled in the Ph.D. program at Carnegie Mellon University, Pittsburgh, PA. His interests include formal verification of hardware and software, programming language design and implementation, and computer typesetting. Kenneth L. McMillan received the B.S. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 1984, and the M.S. degree in electrical engineering from Stanford University, Stanford, CA in 1986. He is currently working on his doctoral dissertation at Carnegie Mellon University, Pittsburgh, PA, on hardware verification. His interests include verification of hardware and communication protocols, noninterleaving models of concurrency, parallel computer architectures, and synthesis of sequential circuits.