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Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation
[article]
2016
arXiv
pre-print
We present a customizable soft architecture which allows for the execution of GPGPU code on an FPGA without the need to recompile the design. Issues related to scaling the overlay architecture to multiple GPGPU multiprocessors are considered along with application-class architectural optimizations. The overlay architecture is optimized for FPGA implementation to support efficient use of embedded block memories and DSP blocks. This architecture supports direct CUDA compilation of integer
arXiv:1606.06454v1
fatcat:ckqxsfqfj5gl7bresimoycrvke