Negative bias temperature instability in SOI and body-tied double-gate FinFETs

Hyunjin Lee, Choong-Ho Lee, Donggun Park, Yang-Kyu Choi
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.  
Negative bias temperature instability (NBTI) characteristics of SOI and body-tied FinFETs are reported for the first time. Both FinFETs show better immunity to NBT stress at a wide fin width (channel thickness) than at a narrow fin width, while the narrow fin FinFET is more robust to hot-carrier injection (HCI) stress. A bodytied FinFET is more stable in response to NBT stress than a SOI FinFET because of non-floating body effects. CMOS lifetime is more degraded by NBT stress than by HCI stress
more » ... than by HCI stress at a narrow fin width and a low operational voltage. Introduction Double-gate structures showed high robustness to shortchannel effects in the nano-scale regime [1] [2] . Previous study showed that the reliability characteristics of CMOS SOI FinFETs by hot-carrier injection (HCI) stress improved with narrow fin width because of reduced impact ionization [3] . A recent report pointed out that NBTI became a major reliability concern for digital as well as analog CMOS circuits [4] . It is timely to study NBTI of double-gate or multiple-gate structures. This work primarily focused on the reliability under NBT stress for doublegate structures: SOI FinFETs and body-tied FinFETs. The fin width is a crucial parameter for determining the device degradation by NBT stress, and a wide fin is preferred to improve the reliability. A simple explanation for device degradation by NBT stress is presented and a specific limiting factor (NBTI or HCI) to govern the device failure is analyzed. Experiments The schematic device structures of the SOI and body-tied FinFET under NBT stress conditions are shown in Fig. 1 . Negative bias was applied to the gate with grounded source/drain for SOI and body-tied FinFETs. Additionally, the body (substrate) was grounded and maintained at 125 o C (high temperature test) for the body-tied FinFETs. Fabrication details were already reported elsewhere [1-2]. The NBTI characteristics had been interpreted using electrochemical reaction models at the SiO 2 /Si interface [5-6]. Hydrogen-passivated dangling silicon bonds are electrically activated by holes at the interface. Then, active interface traps and positive fixed oxide charges are left, while electrons diffuse toward the center of the fin in the SOI FinFETs or the substrate in the body-tied FinFETs. A threshold voltage (V T ) was read at -100nA drain current with -50mV drain bias. V TO is the threshold voltage before NBT stress. The criterion for failure lifetime is 10% degradation of the drain saturation current (I Dsat ), i.e. �I Dsat / I Dsat0 =10%. I Dsat0 is the drain saturation current before DC NBT stress. Results and Discussions The degradation of I Dsat and V T of the PMOS SOI FinFET is accelerated as the DC negative stress voltage is increased or the fin width of FinFET is narrowed (Fig. 2, 3) . When the negative gate bias is applied, the electrons generated by this stress are pushed back to the center of the silicon fin and accumulate as shown in Fig. 4 . As the fin width decreases, the energy band bending due to the accumulated electrons at the center of the silicon fin becomes steeper [7] . The sharp energy band bending increases hole concentration at the interface, and results in accelerating NBTI. This trend is consistent with the previous expectation [8] . Since immunity to NBT stress improves with wider fin width, it should be optimized in balance with short-channel effects (SCEs), to which the wider fin is vulnerable.� Fig. 5 and 6 show the device lifetime of the SOI and the body-tied FinFETs with different fin
doi:10.1109/.2005.1469232 fatcat:34g6chu5ivcgvjkvvq4bwvwwxa