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Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration
2011
2011 Design, Automation & Test in Europe
Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be
doi:10.1109/date.2011.5763179
dblp:conf/date/IndrusiakS11
fatcat:bfa4um6ibzanldzrzeapoearf4