Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture

Ya-Shih HUANG, Yu-Ju HONG, Juinn-Dar HUANG
2009 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative
more » ... hm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
doi:10.1587/transfun.e92.a.3143 fatcat:auox3ejjb5f25eblruugro25vy