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Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
2009
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative
doi:10.1587/transfun.e92.a.3143
fatcat:auox3ejjb5f25eblruugro25vy