Using dynamic cache management techniques to reduce energy in a high-performance processor

Nikolaos Bellas, Ibrahim Hajj, Constantine Polychronopoulos
1999 Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED '99  
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provide the instruction stream to the data path and, when managed properly, it can e ectively eliminate the need for high utilization of the more expensive I-Cache. In this work, we propose, implement, and evaluate a series of run-time techniques for dynamic analysis of the program instruction access behavior, which are then
more » ... ed to proactively guide the access of the L0-Cache. The basic idea is that only the most frequently executed portions of the code should be stored in the L0-Cache since this is where the program spends most of its time. We present experimental results to evaluate the e ectiveness of our scheme in terms of performance and energy dissipation for a series of SPEC95 benchmarks. We also discuss the performance and energy tradeo s that are involved in these dynamic schemes.
doi:10.1145/313817.313856 dblp:conf/islped/BellasHP99 fatcat:pnq4hnsnizgfbn4gw37o5c3cey