A 25 Gb/s 5.8 mW CMOS Equalizer

Jun Won Jung, Behzad Razavi
2015 IEEE Journal of Solid-State Circuits  
Low-power equalization remains in high demand for wireline receivers operating at tens of gigabits per second in copper media. This paper presents a design incorporating a continuoustime linear equalizer and a two-tap half-rate/quarter-rate decision-feedback equalizer that exploits charge steering techniques to reduce the power consumption. Realized in 45 nm technology, the prototype draws 5.8 mW from a 1 V supply and compensates for 24 dB of loss with .
doi:10.1109/jssc.2014.2364271 fatcat:wqb7jeglezfarcdzhwofx2hgye