Automatic Low Power Optimizations during ADL-driven ASIP Design

A. Chattopadhyay, D. Kammler, E. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr
2006 2006 International Symposium on VLSI Design, Automation and Test  
tering into a register whenever a redundant storage takes place. As a result, the internal power and the switching activity of the input Increasing complexity of cutting-edge applications for future and output ports of the register cells get severely reduced. This seembedded systems demand even higherprocessorperformance with lective blocking also reduces power in the downstream logic of the a strong consideration for battery-life. Low power optimization blocked components, since the outputs of
more » ... the blocked components techniques are, therefore, widely applied towards the development remain unaffected for a certain number of clock cycles. ofmodern Application Specific Instruction-Set Processors (ASIPs). Traditionally, RTL-based clock gating is performed manually. Architecture Description Languages (ADLs) offer the ASIP design-With increasing design complexity, automatic clock gating tools ers a quick and optimal design convergence by automatically gener-are getting integrated into the existing commercial synthesis flow. ating the software tool-suite as well as the Register Transfer Level These tools perform clock gating at RTL abstraction. The algo-(RTL) description of the processor The automatically generated rithms typically look for enable flags in the locality of storage eleprocessor description is then subjected to the traditional RTL-based ments or compute the observability of datapath blocks following the synthesis flow. Power-specific optimizations, often found in RTL-storage element. For large datapath blocks, the computation of the based commercial tools, cannot take the full advantage of the ar-observability is demanding in nature and therefore, various approxchitectural knowledge embedded in the ADL description, resulting imate heuristics are used. The ADL-driven processor development in sub-optimal power efficiency. In this paper, we address this is-flow can leverage the architecture-specific knowledge to perform sue by describing an efficient and universal technique ofautomatic highly effective clock gating, as we will show in this paper. Our insertion ofgated clocks during the ADL-based ASIP design flow. clock-gating mechanism is implemented on top of the RTL proces-Experiments with ASIP benchmarks show the dramatic impact of sor synthesis flow from the ADL LISA [11] . The benefits of the our approach by reducing power consumption up to 4100 percent ADL-based clock gating mechanism are evaluated using two modcompared to naive RTL synthesis from ADL description, without ern pipelined embedded processors. The contribution of this paper any incurred overheadfor area and speed. is to present: * A generic ADL-based clock gating methodology * A deterministic, low-complexity clock gating algorithm for 1-4244-0180-
doi:10.1109/vdat.2006.258140 fatcat:ntckq22pnraqdpekaxsieat7ey