A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has beendoi:10.5573/jsts.2014.14.4.376 fatcat:nfwv6g7tsng6pnl3nxnkvdxtly