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In this project an ECG signal processing module will be implemented in VHDL on FPGA platform. The digital filtering will be carried out with low pass FIR architecture. Filters shall filter the 50 Hz coupled noise and other high frequency noises. The filtered signal is subjected to Short Time Fourier transform by which lot of inferences can be made by medical experts. A recorded ECG signal will be used as test input to test the modules implemented on FPGA. The Modelsim Xilinx Edition and Xilinxdoi:10.47893/ijess.2012.1089 fatcat:gko43hosp5fxfc2tmptuyxqk4a