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Synthesis of pipelined DSP accelerators with dynamic scheduling
Proceedings of the 8th international symposium on System synthesis - ISSS '95
To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis will be put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelineddoi:10.1145/224486.224503 dblp:conf/isss/SchaumontVBM95 fatcat:tddaixxn5fbidboovjlcdjsboy