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Lecture Notes in Computer Science
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processor performance. In addition, limitations in interconnect density and bandwidth serve to exacerbate current bottlenecks, particularly as computer architectures continue to reduce in size. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. To facilitatedoi:10.1007/3-540-45591-4_149 fatcat:xcrofkqg55athfqvibc4or6pfu