Three Dimensional VLSI-Scale Interconnects [chapter]

Dennis W. Prather
2000 Lecture Notes in Computer Science  
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processor performance. In addition, limitations in interconnect density and bandwidth serve to exacerbate current bottlenecks, particularly as computer architectures continue to reduce in size. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. To facilitate
more » ... into the current manufacturing infrastructure, our system is monolithically fabricated in the Silicon substrate and preserves scale of integration by using meso-scopic diffractive optical elements (DOEs) for beam routing and fan-out. We believe that this architecture can alleviate the disparity between processor speeds and memory access times while increasing interconnect density by at least an order of magnitude. We are currently working to demonstrate a prototype system that consists of vertical cavity surface emitting lasers (VCSELs), diffractive optical elements, photodetectors, and processor-in-memory (PIM) units integrated on a single silicon substrate. To this end, we are currently refining our fabrication and design methods for the realization of meso-scopic DOEs and their integration with active devices. In this paper, we present our progress to date and demonstrate vertical data transmission using DOEs and discuss the application for our architecture, which is a multi-PIM (MPM) system.
doi:10.1007/3-540-45591-4_149 fatcat:xcrofkqg55athfqvibc4or6pfu