A model checking approach to evaluating system level dynamic power management policies for embedded systems

S.K. Shukla, R.K. Gupta
Sixth IEEE International High-Level Design Validation and Test Workshop  
System Level Power Management policies are typically based on moving the system to various power management states, in order to achieve minimum wastage of power. The major challenge in devising such strategies is that the input task arrival rates to a system is usually unpredictable, and hence the power management strategies have to be designed as on-line algorithms. These algorithms are aimed at optimizing wasted power in the face of nondeterministic task arrivals. Previous works on evaluating
more » ... power management strategies for optimality, have used trace driven simulations, and competitive analysis. In this work, we build upon the competitive analysis based paradigm. Our work views a power management strategy as a winning strategy in a two player game, between the power management algorithm, and a non-deterministic adversary. With the power of non-determinism, we can generate the worst possible scenarios in terms of possible traces of tasks. Such scenarios not only disprove conjectured bounds on the optimality of a power management strategy, but also guides the designer towards a better policy. One could also prove such bounds automatically. To achieve these, we exploit model checkers used in formal verification. However, specific tools which are focused mainly on this kind of power management strategies are under development, which would alleviate some of the state explosion problems inherent in model checking techniques.
doi:10.1109/hldvt.2001.972807 dblp:conf/hldvt/ShuklaG01 fatcat:naicpvkijnhevmecwgzzzrd26a