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A model checking approach to evaluating system level dynamic power management policies for embedded systems
Sixth IEEE International High-Level Design Validation and Test Workshop
System Level Power Management policies are typically based on moving the system to various power management states, in order to achieve minimum wastage of power. The major challenge in devising such strategies is that the input task arrival rates to a system is usually unpredictable, and hence the power management strategies have to be designed as on-line algorithms. These algorithms are aimed at optimizing wasted power in the face of nondeterministic task arrivals. Previous works on evaluating
doi:10.1109/hldvt.2001.972807
dblp:conf/hldvt/ShuklaG01
fatcat:naicpvkijnhevmecwgzzzrd26a