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1993 IEEE International Symposium on Circuits and Systems
We present in this paper systolic arrays with constant number of input/output (I/O) ports for twodimensional (2-D) FIR and IIR filtering. Our design has an array of L × N processing elements (PE's), where L (≤ N) is a technology-dependent parameter related to the number of I/O ports. Each PE in our design has a microprogrammed arithmetic logic unit (ALU), a control unit, a fixed number of I/O buffers, and O (N /L) memory. Our design specializes to a square mesh when L = N, and a linear arraydoi:10.1109/iscas.1993.393706 fatcat:534fe5tiffeepnb4adknwokmue