A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards

Cheng-Hung Lin, Chun-Yu Chen, En-Jui Chang, An-Yeu Wu
2011 2011 International Symposium on Integrated Circuits  
This paper presents a turbo decoder chip design supporting distinct convolutional turbo code schemes in WiMAX and LTE systems. A contention-free vectorizable dual-standard interleaver is proposed to enhance the hardware utilization. Moreover, a warm-up free parallel MAP decoding is proposed to improve the throughput rate. The overall VLSI architecture of the proposed CTC decoder is presented for supporting the WiMAX/LTE systems. This chip fabricated in a core area of 3.38 mm 2 by 90nm CMOS
more » ... ss is measured at 152 MHz with a power consumption of 148.1 mW and a throughput rate of 186.1 Mbps. This chip achieves a high area efficiency of 0.36 bit/mm 2 and a low energy efficiency 0.16 nJ/bit/iteration.
doi:10.1109/isicir.2011.6131904 fatcat:wgu2rqoes5blddfomtpbkpccoa