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2011 International Symposium on Integrated Circuits
This paper presents a turbo decoder chip design supporting distinct convolutional turbo code schemes in WiMAX and LTE systems. A contention-free vectorizable dual-standard interleaver is proposed to enhance the hardware utilization. Moreover, a warm-up free parallel MAP decoding is proposed to improve the throughput rate. The overall VLSI architecture of the proposed CTC decoder is presented for supporting the WiMAX/LTE systems. This chip fabricated in a core area of 3.38 mm 2 by 90nm CMOSdoi:10.1109/isicir.2011.6131904 fatcat:wgu2rqoes5blddfomtpbkpccoa