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FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study
2011
Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)
With the rapid evolution of technology, the latest FPGA architectures such as Virtex series of Xilinx introduced a new feature called Dynamic Partial Reconfiguration (DPR). This technique allows designer to configure a portion of the FPGA while other parts continue to run on the same FPGA. The design of an embedded system based on the DPR functionality is still complex and tedious. The MPEG consortium proposes the Reconfigurable Video Coding (RVC) technology. RVC provides a high level
doi:10.1109/dasip.2011.6136863
dblp:conf/dasip/HentatiANAD11
fatcat:pnfwsoldrbfnpk3o5mhh5oimni