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In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. To determine the biasdoi:10.1145/871506.871590 dblp:conf/islped/LotfiTAS03 fatcat:gibsblywezaqvp4rvwrswy3voy