39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation

Jonathan Bolus, Benton Calhoun, Travis Blalock
2014 Journal of Low Power Electronics and Applications  
A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ∆V T between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ∆V T . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is
more » ... entation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10 −6 , with up to 21 unreliable bits.
doi:10.3390/jlpea4030252 fatcat:o6rigggepnhv3lcbnorutjz3bu