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Architectural support for scalable speculative parallelization in shared-memory multiprocessors
2000
SIGARCH Computer Architecture News
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs
doi:10.1145/342001.363382
fatcat:akzt3gzhhvabxmq6wqydav3v4i