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A power estimation methodology for systemC transaction level models
Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '05
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With the presence of complex cores in current day embedded system-on-chip devices, the problem of complete system level power estimation is gaining significance. Transaction level models for SoCs are gaining increasing attention with emerging architectural modeling standards like SystemC. In this paper we present adoi:10.1145/1084834.1084874 dblp:conf/codes/DhanwadaLN05 fatcat:mhog4fljpnhuvfjuev2pr3g6m4