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Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC
[article]
2022
arXiv
pre-print
Comparators are utilised by Nyquist-rate and oversampling analog to digital converters (ADCs) to accomplish quantization and perhaps sampling. Thus, comparators have a substantial effect on the speed and accuracy of ADCs. This study provides a revised design for a dynamic-latch-based comparator that achieves the lowest latency, maximum area-efficient realisation, reduced power dissipation, and low offset. The proposed circuit has been designed and simulated using GDPK 45 nm standard
arXiv:2209.07259v2
fatcat:noucqevfevgqxpcntst557qblm