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Proceedings of the 2015 International Conference on Artificial Intelligence and Industrial Engineering
The Advanced Encryption Standard (AES) issued by the National Institute of Standards and Technology in 2001 has become the new widely-used symmetric block cipher standard. A lot of efforts have been made on the various hardware implementations of the AES algorithm. Some focus on achieving low-cost constructions, while others focus on designing high throughput. Given the specific requirement of wireless communication and portable devices, this article presents an AES IP core with an acceptabledoi:10.2991/aiie-15.2015.49 fatcat:kwqbhjitdfexxpgd6zw7kiu7b4