A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf
.
An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus
2015
Proceedings of the 2015 International Conference on Artificial Intelligence and Industrial Engineering
unpublished
The Advanced Encryption Standard (AES) issued by the National Institute of Standards and Technology in 2001 has become the new widely-used symmetric block cipher standard. A lot of efforts have been made on the various hardware implementations of the AES algorithm. Some focus on achieving low-cost constructions, while others focus on designing high throughput. Given the specific requirement of wireless communication and portable devices, this article presents an AES IP core with an acceptable
doi:10.2991/aiie-15.2015.49
fatcat:kwqbhjitdfexxpgd6zw7kiu7b4