In MIS-structure, the capacitance depends on applied voltage and its polarity, temperature, 2 oxide thickness and doping level of semiconductor) Coplanar type MIS-SIM structure has been designed and fabricated on low resistivity silicon. The two electrodes are deposited on the thermal oxide grown on silicon. This structure could be analysed by connecting an MIS structure in series with a SIM structure, thus minimising the voltage and temperature variations on capacitance of the MIS-SIM

more »

... as compared to MIS structure. The coplanar type can be used as a descrete capacitor as well as for hybrid circuits where low VCC & TCC are required. FABRICATION Polished n-type silicon wafer of resistivity 0.01 ohm-cm was taken and SiO2 was grown thermally at 1150C. Electrodes pattern were deposited by evaporating 99.999% Aluminium at 10-6 torr vacuum through molybdenum mask. The substrate temperature was kept at 125C during deposition of elec-Etectrodes "/N or P-Siticon FIGURE Structure of coplanar type MIS-SIM capacitor. trodes. The wafer was scribed and diced. The chips were die mounted and wire bonded on TO-5 packages. The capacitor structure is as shown in Figure 1 . MEASUREMENTS AND RESULTS The capacitance of the encapsulated chip capacitor was measured at KHz. The bias voltage during the capacitance measurement was varied from 0 to +100V and no change in the capacitance value was observed within a measurement accuracy of 0.025%. The capacitor was mounted on a temperature jig so that its temperature could be increased from room temperature to 150 degree centigrade. The change in capacitance was less than 5 ppm/degree centrigrade.