System-level design space exploration for heterogeneous parallel dedicated systems

Luigi Pomante, Paolo Serri, Stefano Marchesani
2013 2013 World Congress on Computer and Information Technology (WCCIT)  
This work faces the problem of the HW/SW co-design of dedicated systems based on heterogeneous parallel architectures. In particular, it proposes an extension of a previous system-level design space exploration (DSE) approach able to suggest to the designer an HW/SW partitioning of the application specification and a mapping of the partitioned entities onto an automatically selected heterogeneous multi-processors architecture where each processor could be also homogeneous multi-core. The
more » ... d modeling strategy and the description of the adopted heuristic/metrics represent the core of the paper. on the final system form factor (e.g. on-chip, on-FPGA, on-board) and scope (final product, platform or virtual platform). As stated in the title, this work focuses on dedicated systems. In the scope of this paper, a "dedicated system" is a digital electronic system with custom HW/SW architecture. It is specifically designed to satisfy a priori known application requirements. A dedicated system could be embedded in a more complex system or it could be subjected to real-time constraints. When dedicated systems are also HMPS (D-HMPS), they are so complex that the HW/SW co-design methodology plays a major role in determining the success of a product. In fact, in the past years, a remarkable number of research works have focused on system-level co-design of HMPS (e.g. [5] [6] [7] [8] [9] [10] [11] [12] ). Each of them has proposed a different approach to the design space exploration but always relying on some fixed architectural elements or on the designer's experience. So, at the best of our knowledge, there does not exist a system-level co-design flow that addresses the problem of automatically suggest an HW/SW partitioning of the system functionalities specification, while also mapping the partitioned entities onto an automatically selected heterogeneous multi-processor architecture, where each processor could be also homogeneous multi-core. According with this scenario, this work proposes an extension of the research results described in [17] [7] [20] . The final goal is the extension of an existing design space exploration (DSE) approach that, starting from the system functionalities specification and related requirements, would be able to suggest to the designer: -An HW/SW partitioning of the given system functionalities specification; -A D-HMPS architecture; -A mapping of the partitioned entities onto the proposed architecture able to satisfy imposed requirements. The proposed extension allows to consider, in the same co-design flow, heterogeneous multi-processor architectures where each processor could be also homogeneous multi-core. The paper is organized as follows. Section 2 presents the reference design flow while Section 3 highlights the main modeling issues, specification languages and related "internal models" of representation. The extended reference target HW architecture (described in Section 4) and the description of the proposed heuristics and metrics for design space exploration (Section 5) represent the core of the paper with an illustrative example that allows to clarify the main features of the whole approach. Finally, Section 6 draws out some conclusions and outlines the future work. Reference Co-Design Flow The reference system-level co-design flow (a slight extension of the one in [20]) is shown in Figure 1 : it reports the main codesign steps that are briefly described in the following. Specification The entry point of the proposed co-design flow is the specification of the system functionalities, with related timing constraints, by means of an homogeneous executable specification language to avoid polarizing the design towards hardware or software. Functional Simulation The first step is the Functional Simulation [17] [18] where the system functionalities are simulated to check their correctness with respect to typical input data sets. During this step, important data characterizing the dynamic behavior of the system are also collected: Profiling, Communication and Concurrency. Co-Analysis and Co-Estimation This step of the flow aims at extracting information about the system by statically analyzing the specification. This step is composed of the Co-Analysis [7] [19] and Co-Estimation [17] [21] [22] [23] activities. The former one provides a set of data expressing the Affinity of each system functionality towards a set of processor classes (actually this work considers only COTS GPP, COTS DSP and Custom SPP). The latter provides a set of estimations of the Timing required by each processor class in the set to execute each single statement composing the specification. Finally, another estimation is related to the Size: ROM/RAM bytes needed for SW implementations and equivalent gate (or similar metrics such as number of cells or LUTs) for HW ones.
doi:10.1109/wccit.2013.6618780 fatcat:a2mi2tzzavhs3kiszhmdggxuza