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Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip
2010
2010 39th International Conference on Parallel Processing
As chip multiprocessors transition from multi-core to many-core, on-chip network power is increasingly becoming a key barrier to scalability. Studies have shown that on-chip networks can consume up to 36% of the total chip power, while analysis of network traffic reveals that for extended periods of execution time, network load is well below the network capacity in many applications. In recent studies, researchers have proposed to exploit this temporal variability in network traffic to
doi:10.1109/icpp.2010.52
dblp:conf/icpp/ZafarDP10
fatcat:evwi7sfelzarfg6limxkcfibci