Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by m ultiple variables if they have m utually disjoint lifetime intervals. This approach is eective for signal-ow-like computations such a s v arious DSP algorithms. However, it is not the best for the synthesis of control-dominated circuits, which usually have v ariables/signals of dierent bit-width as well as very

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... lifetime. To g o b ey ond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks. We h a v e implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more eectively than the lifetime-analysis-based approach does. Better register minimization also leads to both smaller area and faster designs.