Implemented 5-Bit 125-Ms/S Successive Approximation Register Adc On Fpga

S. Heydarzadeh, A. Kadivarian, P. Torkzadeh
2012 Zenodo  
Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor switching procedure algorithm .Spartan 3 FPGA is chosen for implementing SAR analog to digital converter algorithm. SAR VHDL program writes in Xilinx and modelsim uses for showing results.
doi:10.5281/zenodo.1075831 fatcat:yqtrxx6dvvbh3fj7dlvrhcyxmq