A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf
.
A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier
2013
International Journal of VLSI Design & Communication Systems
This paper proposes a 2.4 GHz RF CMOS Power amplifier and variation in its main performance parameters i.e, output power, S-parameters and power added efficiency with respect to change in supply voltage and size of the power stage transistor. The supply voltage was varied form 1 V to 5 V and the range of output power at 1dB compression point was found to be from 10.684 dBm to 25.08 dBm respectively. The range of PAE is 16.65 % to 48.46 %. The width of the power stage transistor was varied from
doi:10.5121/vlsic.2013.4509
fatcat:cekh7qiaxzc6pn3r4iiopkuy2u