Internet Archive Scholar

A 1.7mW All Digital Phase-Locked Loop with New Gain Generator and Low Power DCO

Tzu-Chiang Chao, Wei Hwang
2006 IEEE International Symposium on Circuits and Systems  

Preserved Fulltext

fulltext thumbnail
Web Archive Capture PDF (2.3 MB)
https://web.archive.org/web/20170829084706/http://lpsoc.eic.nctu.edu.tw/pub/A%201.7mW%20All%20Digital%20Phase-Locked%20Loop%20with%20New%20Gain%20Generator%20and%20Low%20Power%20DCO.pdf

A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL. The file type is application/pdf.

In this paper, a new architecture and algorithm for Inrual Target all digital phase-locked loop (ADPLL) is proposed. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new MJodified BiEary Search digitally controlled oscillator (DCO) structure for low power, small area is presented and its
more » ... y range is from 200 nleal Yargeet MHz to 750 MHz with a supply voltage 1.2v. The total power fnqency consumption of ADPLL is 1.7mW. This ADPLL has characteristics of fast frequency locking, small hard cost and
doi:10.1109/iscas.2006.1693721 dblp:conf/iscas/ChaoH06 fatcat:dnwr3cbzuzgelkizdwuzw2fecm
Citation

Tzu-Chiang Chao, Wei Hwang. "A 1.7mW All Digital Phase-Locked Loop with New Gain Generator and Low Power DCO." 2006 IEEE International Symposium on Circuits and Systems