On the optimal design of multiple-valued PLAs

T. Sasao
<span title="">1989</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;
This paper describes the design and analysis of three types of multiple-valued PLA's: 'lype 1 PLA's realize functions directly in the form of the MAX of MIN of literal functions and constants. In Type 2 PLA's, the body of the PLA is binary and the output is encoded as a multiple-valued logic value.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/12.21150">doi:10.1109/12.21150</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/t7bbamzepzht7lbefyxlwbrg5i">fatcat:t7bbamzepzht7lbefyxlwbrg5i</a> </span>
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