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In VLSI interconnections are main contributor to delay, energy consumption and area Multiple-valued logic (MVL) allows the reduction of the required number of signals in the circuit, so can be effectively used to reduce the impact of interconnections. In this paper we propose an modified ALU which uses a quaternary logic look up table. The ALU is compatible with standard CMOS processes. The ALU is designed And Simulated Using TANNER. Schematics are designed using S-spice and simulated indoi:10.22214/ijraset.2018.4456 fatcat:2lsifqlip5cf5bkvfyu34mloyy