This paper presents a novel optimal 2-D layout using PN and PNN pattern during placement, we utilize the device merging, abutment and alignment technique to enhance the wire-length and area-efficiency. A placement objective is formulated balancing the symmetry for routing and the area efficiency. To the best of my knowledge, this is the first piece of work that can handle PN and PNN pattern for placement and using device merging, abutment and alignment technique simultaneously. Two cell

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... P3) are used to demonstrate the effectiveness of approach. Moreover, the proposed method generates more area-efficient transistor placements than the conventional method. In experiment we applied PN and PNN pattern for placement of devices with the device merging and abutment technique to attain the results for MTIP3 and IP3 cell 6.5025umsq and 3.114umsq respectively. Result shows that the area of IP3 cell is improved by 50%.