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Architecture Design of The Hardware H.264/AVC Video Decoder The need for real-time video compression systems requires a particular design methodology to achieve high troughput devices. The paper describes the architecture of the H.264/AVC decoder able to support SDTV and HDTV resolutions. The design applies many optimization techniques to reduce the resource consumption and maximize the throughput. The archietcture is verified with the software reference model JM16 and synhesized for FPGAdoi:10.2478/v10177-010-0039-7 fatcat:nhctikbqmngk3atpcrzzejqalu