Montgomery Multiplication Using Vector Instructions [chapter]

Joppe W. Bos, Peter L. Montgomery, Daniel Shumow, Gregory M. Zaverucha
2014 Lecture Notes in Computer Science  
In this paper we present a parallel approach to compute interleaved Montgomery multiplication. This approach is particularly suitable to be computed on 2-way single instruction, multiple data platforms as can be found on most modern computer architectures in the form of vector instruction set extensions. We have implemented this approach for tablet devices which run the x86 architecture (Intel Atom Z2760) using SSE2 instructions as well as devices which run on the ARM platform (Qualcomm
more » ... NVIDIA Tegra 3 and 4) using NEON instructions. When instantiating modular exponentiation with this parallel version of Montgomery multiplication we observed a performance increase of more than a factor of 1.5 compared to the sequential implementation in OpenSSL for the classical arithmetic logic unit on the Atom platform for 2048-bit moduli.
doi:10.1007/978-3-662-43414-7_24 fatcat:xl677jumtvejtg6x2mldra7lrm