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Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique
2013
International Journal of Computer Applications
In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches.
doi:10.5120/11608-6984
fatcat:7pm7bgp2i5agvptbschh36vwj4