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Power Integrity Analysis Of Power Delivery System In High Speed Digital Fpga Board
2016
Zenodo
Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current
doi:10.5281/zenodo.1127121
fatcat:5vfqrcff3vc7nmwp3xpmfh5vnq