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Test power has become a critical issue, especially for lowpower devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capturesafety checking mandatory for test vectors. However, previous capturesafety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit.doi:10.1587/transinf.e96.d.2003 fatcat:pwwr2rd4sba43k35ppb5jqi7gy