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For inverters, a phase-locked loop (PLL) is usually needed for the grid synchronization. Typically, for the single-phase inverters, the orthogonal-signal-generators based PLLs (e.g., delay-based PLL) can be used. However, if the grid at the point of common coupling (PCC) exhibits a large grid impedance, the inverter may not work well or even be unstable. In order to work satisfactorily in the very weak grid, this study aims to formulate a robust PLL. At first, by modeling the inverter outputdoi:10.1109/access.2020.2995624 fatcat:3nbgsvv3c5d5nehay2smu4zjsy