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ASR: Adaptive Selective Replication for CMP Caches
2006
Microarchitecture (MICRO), Proceedings of the Annual International Symposium on
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache capacity and minimize off-chip misses. Others use private L2 caches, replicating data to limit the delay due to global wires and minimize cache access time. Recent hybrid proposals use selective replication to balance latency and capacity, but their static replication rules result in performance degradation for some
doi:10.1109/micro.2006.10
dblp:conf/micro/BeckmannMW06
fatcat:ybh52lm5ajenvezppy2f2rbjpy