FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

Vinod Kapse, Bhavana Jharia, S. S. Thakur
2012 International Journal of Modern Education and Computer Science  
This paper presents a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions. Analysis shows that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A FPGA based pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea, implemented on CycloneII-EP2C70F896C8. The
more » ... r is capable of processing fuzzified input. The proposed controller is designed for 2-input 1output with maximum clock rate is 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules, respectively.
doi:10.5815/ijmecs.2012.07.04 fatcat:jbhx6ifdobchnhsffanmsr477a