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Lecture Notes in Computer Science
Model checking is an automatic verification technique for finite state concurrent systems such as sequential circuit designs and communication protocols. Specifications are expressed in propositional temporal logic. An exhaustive search of the global state transition graph or system model is used to determine if the specification is true or not. If the specification is not satisfied, a counterexample execution trace is generated if possible. By encoding the model using Binary Decision Diagramsdoi:10.1007/3-540-69778-0_3 fatcat:flyys7zuefhpzou562dwv7hufa