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A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
2006
Proceedings of the 43rd annual conference on Design automation - DAC '06
integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3-D technology under the influence of such thermal constraints. Using a
doi:10.1145/1146909.1147160
dblp:conf/dac/LoiASLSB06
fatcat:7cuyik4tyjajnnyon4evhetnna